Integrated circuit devices using self-aligned shallow trench isolation technology may provide a reduced number of fabrication steps during manufacture of the integrated circuit device, enhanced reliability of a gate oxide layer and/or narrower threshold voltage distribution in a cell array. Accordingly, to improve performance of conventional nonvolatile memory devices, self-aligned shallow trench isolation technology has been applied to highly integrated nonvolatile memory devices typically requiring low fabrication costs and high reliability.
FIGS. 1 through 3 illustrate aspects of conventional nonvolatile memory devices. FIG. 1 is a top plan view illustrating conventional nonvolatile memory devices, FIGS. 2 and 3 are cross-sectional views illustrating conventional nonvolatile memory devices, taken along lines A-A′ and B-B′ of FIG. 1, respectively.
Referring now to FIGS. 1 through 3, a device isolation pattern is provided on an integrated circuit substrate 2 to define a plurality of active regions. A control gate electrode 16 crosses over the device isolation pattern. A floating gate pattern 9 is disposed between the control gate electrode 16 and the active regions.
The device isolation pattern includes a trench oxide layer 6 and an insulating pattern 14. The trench oxide layer 6 is provided on sidewalls of a trench region provided in the integrated circuit substrate. The insulating pattern 14 is provided in the trench region. The floating gate pattern 9 includes a lower gate pattern 4a and an upper gate pattern 8. The lower gate pattern 4a is provided between the device isolation patterns, and the upper gate pattern 8 is provided on the lower gate pattern 4a. A portion of the upper gate pattern 8 may extend on a surface of the device isolation pattern. The blocking insulating pattern 13 is disposed between the control gate electrode 16 and the floating gate pattern 9. The blocking insulating pattern 13 typically includes first 10, second 11 and third 12 layers of silicon oxide, silicon nitride and silicon oxide, respectively. The control gate electrode 16 typically includes first and second layers, for example, a polysilicon layer 14 on the blocking insulating pattern 13 and a metal silicide layer 15 on the polysilicon layer 14.
As further illustrated in FIG. 3, the nonvolatile memory device further includes a tunnel insulating pattern 3 and source/drain regions S/D. The tunnel insulating pattern 3 is provided between the floating gate pattern 9 and the integrated circuit substrate 2. The source/drain regions S/D are provided in the integrated circuit substrate 2 adjacent to the floating gate pattern 9 to be aligned to sidewalls of the floating gate pattern 9. Referring again to FIG. 2, conventional nonvolatile memory devices may include a bird's beak 7 (thickening of the trench oxide layer 6) at the edge of the tunnel insulating pattern 3 adjacent to the trench oxide layer 6.
FIG. 4 illustrates a cross-sectional view illustrating a process forming the conventional nonvolatile memory devices, taken along line A-A′ of FIG. 1. Referring now to FIG. 4, methods of forming conventional nonvolatile devices include forming the tunnel insulating pattern 3, a lower conductive pattern 4 and a hard mask pattern 5 on the integrated circuit substrate 2. A trench may be formed on the integrated circuit substrate and may be aligned to sidewalls of the hard mask pattern 5. A thermal oxidization process may be applied to the integrated circuit substrate 2 including the trench to form the trench oxide layer 6 on sidewalls and a bottom of the trench. The thermal oxidization process may reduce an etch damage of the sidewalls of the trench. The sidewalls of the lower conductive pattern 4 may be oxidized, resulting in the bird's beak 7 at the edge of the tunnel insulating pattern 3, which is caused by an oxygen atom diffused through interfaces between the lower conductive pattern 4, the tunnel insulating pattern 3 and the integrated circuit substrate 2.
Referring again to FIG. 3, the nonvolatile memory device may include a gate sidewall oxide layer 19 on the sidewalls of the control gate electrode 16 and the floating gate pattern 9. The gate sidewall oxide layer 19 may be formed during a gate sidewall oxidization process to cure an etch damage of the sidewalls of the control gate electrode and the floating gate pattern. The gate sidewall oxide layer 19 may reduce the amount of etch damage of the sidewalls of the control gate electrode 16 and the floating gate pattern 9. According to conventional methods of fabrication, during formation of the gate sidewall oxide layer 19, oxygen atoms may be diffused through an interface of the blocking insulating pattern 13 to oxidize the control gate electrode 16 and the floating gate pattern 9. Accordingly, the silicon oxide layer at the edge 18 of the blocking insulating pattern 13 may become thicker (form a bird's beak) relative to the other portions of the blocking insulating pattern 13. Furthermore, the oxygen atom may be diffused through an interface of the tunnel insulating pattern 3 adjacent to the source/drain regions S/D. Thus, the edge 17 of the tunnel insulating pattern adjacent to the source/drain region S/D may also become thicker (form a bird's beak).
The nonvolatile memory device may use a charge trap pattern as a substitute of the floating gate pattern. The charge trap pattern may be aligned to the control gate electrode 6. A gate sidewall oxidation process may be performed to reduce an etch damage of sidewalls of the charge trap pattern, the blocking insulating pattern and the control gate electrode. The gate sidewall oxidation process may form a gate sidewall oxide layer on sidewalls of the tunnel insulating pattern, the charge trap pattern, the blocking insulating pattern and the control gate electrode. Accordingly, an oxide layer at the edges of the tunnel insulating pattern, the charge trap pattern and the blocking insulating pattern may become thicker (form bird's beaks) relative to the other portions of the tunnel insulating pattern, the charge trap pattern and the blocking insulating pattern.
The presence of the bird's beak on the tunnel insulating pattern, the charge trap pattern and the blocking insulating pattern may cause the reliability of the nonvolatile memory device to deteriorate and may cause an increase in the distribution of the threshold voltage in the cell array. In particular, the presence of the bird's beak on the blocking insulating pattern may lower a coupling ratio of the nonvolatile memory device, an erase speed of the nonvolatile memory device and a write speed of the nonvolatile memory device.